The present invention relates to a complementary logic circuit and more particularly but not exclusively to a level shifting circuit for converting a received input signal from a first voltage level to a second voltage level.
In integrated circuits there often exists a need to convert a logic signal from a first voltage level to a second, higher voltage level. One such example where this need arises is when it is necessary to provide an output signal from an integrated circuit at a high voltage level to drive a peripheral circuit or output device. It is quite common for the peripheral circuits or output devices associated with the integrated circuit to operate at voltages measured in tens of volts, whereas the logic levels produced by the integrated circuit itself are commonly at approximately one and a half volts.
There are known circuits which have been provided for converting an input signal received from an integrated circuit at a low voltage level and producing at an output a signal having the same logic value as the input signal and at a substantially higher voltage. An example of one such circuit is shown in FIG. 1 and will now be discussed.
FIG. 1 shows a level shifting circuit having two circuit branches, a left hand circuit branch 1 and a right hand circuit branch 2. Each circuit branch comprises a NMOS field effect transistor (FET) 3,4 having a source connected to ground voltage. Each circuit branch further comprises a PMOS FET 5,6 having a source connected to an upper supply voltage Vdd. The upper supply voltage Vdd is at the second higher voltage level to which it is desired to convert input signals. The drains of the PMOS FETs 5,6 and the NMOS FETs 3,4 in each circuit branch 1,2 are connected together. The gate of the PMOS FET 5 in the left hand circuit branch 1 is connected to the drain of the NMOS FET 4 in the right hand circuit branch 2 and the gate of the PMOS FET 6 in the right hand circuit branch 2 is connected to the drain of the NMOS FET 3 in the left hand circuit branch 1. The output 8 of the circuit is also connected to the drain of the NMOS FET 4 of the right hand circuit branch. An input signal at the first voltage level is input to circuit at the input i/P. The input i/P is connected to the gate of the NMOS transistor 3 of the left hand circuit branch 1 and is connected to the input of an inverter 7, the output of the inverter 7 being connected to the gate of the NMOS transistor 4 of the right hand circuit branch 2.
The operation of the known circuit shown in FIG. 1 is as follows. Assume that the input signal is initially at a logic level high. Therefore the NMOS transistor 3 of the left hand circuit branch 1 is conductive and the NMOS transistor 4 of the right hand circuit branch 2 is non-conductive. The drain 9 of the NMOS transistor 3 of the left hand circuit branch 1 is therefore held at ground voltage which in turn provides a gate signal to the PMOS transistor 6 of the right hand circuit branch 2 so that this PMOS transistor 6 is conductive. As the PMOS transistor 6 of the right hand circuit branch 2 is conductive, the drain 10 of the NMOS transistor 4 of the right hand circuit branch 2 is held at Vdd volts and a high gate signal is applied to the PMOS transistor 5 of the left hand circuit branch 1, rendering the other PMOS transistor 5 non-conductive. Hence the output o/p is a logic level high, at a higher voltage level supplied by Vdd.
Assume now that the input signal at the input i/p changes to a logic level zero. The NMOS transistor 3 of the left hand circuit branch is now non-conductive while the other NMOS transistor 4 starts to switch to the conductive state. However, for this NMOS transistor 4 to fully turn on, the voltage at the drain 10 of the NMOS transistor 4 of the right hand circuit branch 2 must be pulled down to ground voltage against the action of the PMOS transistor 6 of the right hand circuit branch 2 which is still conductive, and therefore is attempting to maintain this voltage at Vdd volts. When this voltage has fallen by a voltage level equivalent to the threshold voltage of the PMOS transistor 5 of the left hand circuit branch, the PMOS transistor 5 will begin to switch to the conductive state. At this point the voltage at the drain 9 of the NMOS transistor 3 of the left hand circuit branch begins to rise towards Vdd due to the action of the increasing conductivity of the PMOS transistor 5 of the left hand circuit branch 1. This in turn begins to switch the other PMOS transistor 6 into the non-conducting state. As the PMOS transistor 6 of the right hand circuit branch turns off, the NMOS transistor 4 of the right hand circuit branch is able to pull the voltage at its drain 10 fully to ground voltage. Hence the PMOS transistor 5 of the left hand circuit branch is switched fully on, the drain 9 of the NMOS transistor of the left hand circuit branch is pulled up fully to a voltage level Vdd and the other PMOS transistor 6 of the right hand circuit branch is turned fully off.
For the circuit shown in FIG. 1 to work both NMOS transistors 3,4 must be capable ofxe2x80x9cover poweringxe2x80x9d the respective PMOS transistors 5,6. It will be appreciated that this requires the drain/source saturation current of the PMOS transistors (referred to as Idd_PMOS) for a drain/source voltage Vds and gate/source voltage Vgs equal to a supply voltage at the second, high voltage level, Vdd_high, must be less than the drain/source current of the NMOS transistors, Idd_NMOS, for a drain/source voltage Vds equal to the supply voltage Vdd_high and a gate/source voltage Vgs equal to a supply voltage at the first, low voltage level, Vdd_low. This can be expressed as Idd_PMOS (Vds=Vgs=Vdd_High) less than Idd_NMOS (Vgs=Vdd_Low, Vds=Vdd_High) for all constitutions of the circuit including strong_PMOS/weak_NMOS. This requires the PMOS field effect transistors to be substantially smaller than the NMOS transistors and subsequently the rise time of the PMOS transistors is large. The large rise time reduces the switching speed of the level shifting circuit, thus limiting the speed at which an integrated circuit which includes such a level shifting circuit can operate.
It will be appreciated that if the input signal to the NMOS transistor 3 of the left hand circuit branch is inverted rather than the input to the NMOS transistor 4 of the right hand circuit branch then the output of the circuit will be the inverse of the input signal i.e. the circuit will operate as a logic invertor, as well as a level shifter.
It will be further appreciated that the circuit shown in FIG. 1 has a resultant current flow when the input signal input to the circuit at the input i/P changes from a first logic state to a second logic state. That is to say the circuit only consumes power during switching. Therefore, in the circuit shown in FIG. 1, the relatively slow switching speed of the circuit increases the time period during which there is a resultant current flow in the circuit and hence increases the power consumption of the circuit.
It is an aim of embodiments of the present invention to provide a complementary logic circuit which mitigates against the disadvantages of known level shifting circuits.
According to the present invention there is provided a complementary logic circuit having an input, an output and comprising first and second circuit branches, each circuit branch having: a first transistor of a first conductivity type having a first terminal connected to a first supply node, a control terminal and a second terminal; a second transistor of the first conductivity type having a first terminal connected to the second terminal of the first transistor, a control terminal connected to a second supply node, and a second terminal; and a third transistor of a second conductivity type different to said first conductivity type, having a first terminal connected to the second terminal of the second transistor, a control terminal, and a second terminal connected to the second supply node, wherein: the control terminals of said first transistors of respective first and second circuit branches are coupled to said input; said output is connected to one of the first and second terminals of or of said third transistors, and the control terminals of said third transistors of said first and second circuit branch are connected to the second terminals of said first transistors of said second and first circuit branch respectively.
To provide a better understanding of the present invention a preferred embodiment will now be described in further detail by way of example with reference to the following Figures, in which;